Three state gates have an output which is capable of assuming an active high, an active low, or a high impedance state. Conventional bipolar three state gates comprise a push-pull output driver stage, a phase splitting stage, and a high impedance enable stage. The push-pull output driver stage comprises a dual transistor arrangement wherein a first NPN transistor is coupled between a DC voltage supply and an output load, and a second NPN transistor is coupled between the output load and ground. In operation, a high output voltage is realized at the output terminal by turning on the first NPN transistor and turning off the second NPN transistor; a low output voltage is realized by turning off the first NPN transistor and turning on the second NPN transistor; and a high impedance is achieved by turning off both transistors. The phase splitting stage comprises a bipolar transistor coupled between the bases of the first and second NPN transistors that would selectively turn on one of the first and second NPN transistors. A high impedance enable stage typically comprises diodes coupled to both the phase splitting stage and the output stage for disabling the first and second NPN transistors.
One previously known CMOS three state gate comprises a push-pull output driver stage and an input stage. The push-pull output driver stage comprises a dual transistor arrangement wherein a P-channel transistor is coupled between voltage supply V.sub.DD and an output load, and an N-channel transistor is coupled between the output load and voltage supply V.sub.SS. In operation, a high output voltage is realized at the output terminal by turning on the P-channel transistor and turning off the N-channel transistor; a low output voltage is realized by turning off the P-channel transistor and turning on the N-channel transistor; and a high impedance is achieved by turning off both transistors. The input stage comprises CMOS transistors coupled to the gates of the P-channel and N-channel transistors that would selectively turn on one of the P-channel and N-channel transistors or disable both the P-channel and N-channel transistors.
The bipolar three state gate provides fast gate speeds, high drive capability, improved output signal switching characteristics and reduced delay per unit load, but has lower noise immunity and higher power requirements than the conventional CMOS three state gate. The CMOS three state gate provides high noise immunity and low power requirements, but is generally slower and has lower drive capability than the conventional bipolar three state gate.
Thus, a need exists for an imprcved three state gate having high noise immunity, low power requirements, high drive capability, and improved output signal switching characteristics.